Wiring board

ABSTRACT

A wiring board includes an insulating layer, a thin film capacitor laminated on the insulating layer, an interconnect layer electrically connected to the thin film capacitor, and an encapsulating resin layer laminated on the thin film capacitor. The interconnect layer includes a pad protruding from the thin film capacitor. The encapsulating resin layer is a mold resin having a non-photosensitive thermosetting resin as a main component thereof. The encapsulating resin layer exposes a top surface of the pad, and covers at least a portion of a side surface of the pad.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims priority to Japanese PatentApplication No. 2021-079993, filed on May 10, 2021, the entire contentsof which are incorporated herein by reference.

FIELD

The present disclosure relates to wiring boards, and methods formanufacturing wiring boards.

BACKGROUND

Conventionally, as wiring boards on which electronic components, such assemiconductor chips or the like are mounted, there is a known wiringboard having multiple interconnect layers and multiple insulating layersthat are alternately laminated by a build-up method, in order toincrease the density of interconnect patterns. This type of wiring boardhaving a configuration in which a thin film capacitor is embedded insideto improve transmission characteristics has been studied. This type ofwiring board is proposed in Japanese Laid-Open Patent Publication No.2019-179865, for example.

In order to further improve the transmission characteristics of thewiring board, the thin film capacitor needs to be provided at a topsurface closer to a semiconductor chip. However, when mounting thesemiconductor chip on the wiring board having the thin film capacitorprovided at the top surface, the thin film capacitor may be damaged dueto thermal stress or pressure during mounting.

SUMMARY

Accordingly, it is one object of the present disclosure to provide awiring board capable of reducing damage to a thin film capacitor.

According to one aspect of embodiments of the present disclosure, awiring board includes an insulating layer; a thin film capacitorlaminated on the insulating layer; an interconnect layer electricallyconnected to the thin film capacitor; and an encapsulating resin layerlaminated on the thin film capacitor, wherein the interconnect layerincludes a pad protruding from the thin film capacitor, theencapsulating resin layer is a mold resin having a non-photosensitivethermosetting resin as a main component thereof, and the encapsulatingresin layer exposes a top surface of the pad, and covers at least aportion of a side surface of the pad.

The object and advantages of the embodiments will be realized andattained by means of the elements and combinations particularly pointedout in the claims.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and notrestrictive of the invention, as claimed.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A and FIG. 1B are cross sectional views illustrating an example ofa wiring board according to a first embodiment;

FIG. 2A, FIG. 2B, and FIG. 2C are diagrams (part 1) illustrating anexample of a manufacturing process of the wiring board according to thefirst embodiment;

FIG. 3A and FIG. 3B are diagrams (part 2) illustrating the example ofthe manufacturing process of the wiring board according to the firstembodiment;

FIG. 4A, FIG. 4B, and FIG. 4C are diagrams (part 3) illustrating theexample of the manufacturing process of the wiring board according tothe first embodiment;

FIG. 5A, FIG. 5B, and FIG. 5C are diagrams (part 4) illustrating theexample of the manufacturing process of the wiring board according tothe first embodiment;

FIG. 6A and FIG. 6B are diagrams (part 5) illustrating the example ofthe manufacturing process of the wiring board according to the firstembodiment;

FIG. 7A and FIG. 7B are diagrams (part 6) illustrating the example ofthe manufacturing process of the wiring board according to the firstembodiment;

FIG. 8 is a cross sectional view illustrating an example of a laminatedwiring board according to a first application example of the firstembodiment;

FIG. 9 is a cross sectional view illustrating an example of asemiconductor device according to a second application example of thefirst embodiment; and

FIG. 10 is a cross sectional view illustrating an example of the wiringboard according to a first modification of the first embodiment.

DESCRIPTION OF EMBODIMENTS

Preferred embodiments of the present invention will be described withreference to the accompanying drawings. In the drawings, thoseconstituent elements that have substantially the same functionalconfigurations are designated by the same reference numerals, and arepeated description of the same parts may be omitted.

First Embodiment

[Configuration of Wiring Board]

First, a configuration of a wiring board according to a first embodimentwill be described. FIG. 1A and FIG. 1B are cross sectional viewsillustrating an example of the wiring board according to the firstembodiment. FIG. 1B is an enlarged view of a thin film capacitor 20 anda vicinity thereof in FIG. 1A.

As illustrated in FIG. 1A and FIG. 1B, a wiring board 1 according to thefirst embodiment includes a first interconnect structure 1L, a secondinterconnect structure 1H laminated on the first interconnect structure1L, and an encapsulating resin layer 34 laminated on the secondinterconnect structure 1H. A planar shape of the wiring board 1 may be asquare shape or a rectangular shape, for example. However, the planarshape of the wiring board 1 is not limited to such shapes, and thewiring board 1 may have an arbitrary planar shape.

The first interconnect structure 1L includes a low-density interconnectlayer formed with an interconnect layer having a lower interconnectdensity than the second interconnect structure 1H. The firstinterconnect structure 1L includes an interconnect layer 11, aninsulating layer 12, and an interconnect layer 13. In contrast, thesecond interconnect structure 1H includes a high-density interconnectlayer formed with an interconnect layer having a higher interconnectdensity than the first interconnect structure 1L. The secondinterconnect structure 1H includes an interconnect layer 14, aninsulating layer 15, an interconnect layer 16, an insulating layer 17,an interconnect layer 18, an insulating layer 19, the thin filmcapacitor 20, and an interconnect layer 31.

In the present embodiment, for the sake of convenience, a top-side orone side of the wiring board 1 refers to the side of the wiring board 1provided with an encapsulating resin layer 34, and a bottom-side or theother side of the wiring board 1 refers to the side of the wiring board1 provided with the insulating layer 12. In addition, one surface or atop surface of each part of the wiring board 1 refers to the surface onthe side provided with the encapsulating resin layer 34, and the othersurface of a bottom surface of each part of the wiring board 1 refers tothe surface on the side provided with the insulating layer 12. However,the wiring board 1 may be used in an upside-down state, or may bedisposed at an arbitrary angle. Further, a plan view of an object refersto a view of the object viewed in a normal direction to a top surface 34a of the encapsulating resin layer 34, and a planar shape refers to ashape of the object in the plan view, that is, the shape of the objectviewed in the normal direction to the top surface 34 a of theencapsulating resin layer 34.

The interconnect layer 11 is a lowermost interconnect layer that isexposed at a bottom surface of the insulating layer 12, and a topsurface and a side surface of the interconnect layer 11 are covered bythe insulating layer 12. A bottom surface of the interconnect layer 11is exposed from the a bottom surface 12 b of the insulating layer 12 ata position recessed toward the interconnect layer 13, for example.However, the bottom surface of the interconnect layer 11 may coincidewith the bottom surface 12 b of the insulating layer 12, as required.Alternatively, a portion of the side surface and the bottom surface ofthe interconnect layer 11 may protrude downward from the bottom surface12 b of the insulating layer 12.

The interconnect layer 11 is a circular pad having a circular planarshape with a diameter of approximately 150 μm, for example, but mayinclude an interconnect pattern. A spacing between adjacent interconnectlayers 11 may be approximately 200 μm, for example. Examples of amaterial used for the interconnect layer 11 include copper (Cu) or thelike, for example. Ae thickness of the interconnect layer 11 may be in arange of approximately 10 μm to approximately 20 μm, for example. Theinterconnect layer 11 can be used as an external connection terminal (orpad) for making electrical connection with other wiring boards.

A surface treatment layer 110 may be formed on the bottom surface of theinterconnect layer 11. Examples of the surface treatment layer 110include an Au layer, a Ni/Au layer (a metal layer in which a Ni layerand a Au layer are laminated in this order), a Ni/Pd/Au layer (a metallayer in which a Ni layer, a Pd layer, and a Au layer are laminated inthis order), or the like. In addition, the bottom surface of theinterconnect layer 11 may be subjected to an anti-oxidation treatment,such as an Organic Solderability Preservative (OSP) treatment or thelike.

The insulating layer 12 covers the top surface and the side surfaces ofthe interconnect layer 11. The insulating layer 12 includes anon-photosensitive thermosetting resin as a main component thereof, anda reinforcing member 128. The insulating layer 12 may be configured toinclude the reinforcing member 128 impregnated with thenon-photosensitive thermosetting resin. Herein, “includes anon-photosensitive thermosetting resin as a main component thereof”means that other components, such as a filler or the like, may beincluded in addition to the thermosetting resin.

Examples of the non-photosensitive thermosetting resin used for theinsulating layer 12 include epoxy resins, imide resins, phenolic resins,cyanate-based resins, or the like, for example. Examples of thereinforcing member 128 include woven and non-woven fabrics such as glassfiber, carbon fiber, aramid fiber, or the like, for example. Examples ofthe filler included in the insulating layer 12 include silica (SiO₂),kaolin (Al₂Si₂O₅ (OH₄)), talc (Mg₃Si₄O₁₀(OH₂)), alumina (Al₂O₃), or thelike, for example. In addition, the filler may include a mixture of suchmaterials.

A thickness of the insulating layer 12 may be in a range ofapproximately 60 μm to approximately 70 μm, for example. A thermalexpansion coefficient (or coefficient of thermal expansion) of theinsulating layer 12 may be in a range greater than or equal to 5 ppm/°C. and less than or equal to 10 ppm/° C. The thermal expansioncoefficient of the insulating layer 12 may be adjusted to apredetermined value by a filler content, a composition of the insulatingresin, or the like, for example. The thermal expansion coefficient ofthe insulating layer 12 is lower than the thermal expansion coefficientof each of the insulating layers 15, 17, and 19.

The interconnect layer 13 is a via interconnect embedded in theinsulating layer 12. More particularly, the interconnect layer 13 is avia interconnect filled inside a via hole 12 x that penetrates theinsulating layer 12 and exposes the top surface of the interconnectlayer 11, and this via interconnect is electrically connected to theinterconnect layer 11. The via hole 12 x may be a recess having aninverted truncated cone shape. A diameter of a first opening of the viahole 12 x which opens at the insulating layer 15, may be greater than adiameter of a second opening of the via hole 12 x which opens at the topsurface of the interconnect layer 11. A bottom surface of the secondopening of the via hole 12 x is formed by the top surface of theinterconnect layer 11. The first opening of the via hole 12 x may have adiameter in a range of approximately 60 μm to approximately 70 μm, forexample.

A top surface of the interconnect layer 13, which is the viainterconnect, is exposed from the top surface 12 a of the insulatinglayer 12. The top surface of the interconnect layer 13 may coincide withthe top surface 12 a of the insulating layer 12, for example. The topsurface of the interconnect layer 13 is directly bonded to a bottomsurface of the interconnect layer 14. In addition, a bottom surface ofthe interconnect layer 13 is directly bonded to the interconnect layer11 within the insulating layer 12. A material used for the interconnectlayer 13 may be similar to the material used for the interconnect layer11, for example.

In the present embodiment, the interconnect layer 13 is formed solely ofthe via interconnect formed in the via hole 12 x of the insulating layer12. In other words, the interconnect layer 13 includes no interconnectpattern formed integrally on the top surface 12 a of the insulatinglayer 12. The interconnect layer 13 and interconnect layer 14 areelectrically connected, but are not formed integrally. Moreparticularly, in a method for manufacturing the wiring board which willbe described later, when the interconnect layer 14 is formed by asemi-additive method, a seed layer is interposed between the top surfaceof the interconnect layer 13 and a bottom surface of the interconnectlayer 14. The reason for employing such a configuration is to form ahigh-density interconnect pattern, having a line-and-space (L/S) ofapproximately 3 μm/3 μm, as the interconnect layer 14 described below. Adescription of the interconnect layer 14 in more detail will be givenlater in conjunction with the method for manufacturing the wiring board1.

The interconnect layer 14 is formed on the top surface 12 a of theinsulating layer 12. The interconnect layer 14 is formed directly on thetop surface 12 a of the insulating layer 12, and includes aninterconnect, such as interconnect patterns and pads, electricallyconnected to the interconnect layer 11 through the interconnect layer13. In other words, a portion of the bottom surface of the interconnectlayer 14 is in contact with the top surface of the interconnect layer13, and the interconnect layer 14 and the interconnect layer 13electrically connected to each other. A material, such as copper (Cu) orthe like, for example, may be used for the interconnect layer 14. Theinterconnect layer 14 may be a laminated film including a plurality oflaminated conductor layers.

The interconnect layer 14 has a higher interconnect density, that is, anarrower line-and-space (L/S), than the interconnect layer 11. Further,the interconnect layer 14 is thinner than the interconnect layer 11. Inthis specification, an interconnect layer having a line-and-space (L/S)less than or equal to 8 μm/8 μm is regarded as an interconnect layerhaving a high interconnect density. The line-and-space (L/S) of theinterconnect layer 14 may be in a range of approximately 1 μm/1 μm toapproximately 3 μm/3 μm, for example. The thickness of the interconnectlayer 14 may be in a range of approximately 1 μm to approximately 3 μm,for example.

The line of the line-and-space (L/S) represents a trace width (or widthof interconnect), and the space of the line-and-space (L/S) represents aspacing of adjacent interconnects (or space between adjacentinterconnects). For example, when the line-and-space (L/S) isrepresented as 2 μm/2 μm, the trace width is 2 μm, and the spacing ofthe adjacent interconnects is 2 μm.

The insulating layer 15 is an insulating layer that includes aphotosensitive resin as a main component thereof. The insulating layerthat “includes a photosensitive resin as a main component” means thatthe insulating layer may include components other than thephotosensitive resin, such as a filler or the like. For example, theinsulating layer 15 may include a filler, such as silica (SiO₂) or thelike.

The insulating layer 15 is formed on the top surface 12 a of theinsulating layer 12, so as to cover the interconnect layer 14. Examplesof the photosensitive resin used for the insulating layer 15 include aninsulating resin, such as phenolic resins, polyimide resins, or thelike, for example. A thickness of the insulating layer 15 may be in arange of approximately 5 μm to approximately 10 μm, for example. Athermal expansion coefficient of the insulating layer 15 may be in arange greater than or equal to 40 ppm/° C. and less than or equal to 60ppm/° C., for example. The thermal expansion coefficient of theinsulating layer 15 may be adjusted to a predetermined value by a fillercontent, a composition of the insulating resin, or the like, forexample.

However, in the insulating layer 15 having the photosensitive resin asthe main component thereof, there is a limit (that is, upper limit) tothe amount of the filler that can be included (that is, the fillercontent), because an exposure becomes impossible when the filler contentis high. Accordingly, the thermal expansion coefficient of theinsulating layer 15, having the photosensitive resin as the maincomponent thereof, has a tendency to become higher than the thermalexpansion coefficient of the insulating layer 12, having thenon-photosensitive thermosetting resin as the main component thereof,and higher than the thermal expansion coefficient of the encapsulatingresin layer 34.

The interconnect layer 16 is formed on one side of the insulating layer15, and is electrically connected to the interconnect layer 14. Theinterconnect layer 16 includes a via interconnect filling the via hole15 x which penetrates the insulating layer 15 to expose a top surface ofinterconnect layer 14, and an interconnect pattern formed on a topsurface of insulating layer 15. The via hole 15 x may be a recess havingan inverted truncated cone shape. A diameter of a first opening of thevia hole 15 x which opens at the insulating layer 17, may be greaterthan a diameter of a second opening of the via hole 15 x which opens atthe top surface of the interconnect layer 14. A bottom surface of thesecond opening of the via hole 15 x is formed by the top surface of theinterconnect layer 14. The first opening of the via hole 15 x may have adiameter in a range of approximately 10 μm to approximately 20 μm, forexample. A material used for the interconnect layer 16, and a thicknessof the interconnect pattern forming the interconnect layer 16 may besimilar to those of the interconnect layer 14, for example.

The line-and-space (L/S) of the interconnect layer 16 may be in a rangeof approximately 1 μm/1 μm to approximately 3 μm/3 μm, for example, butthis line-and-space (L/S) may be narrower than that of the interconnectlayer 14. In other words, the top surface 12 a of the insulating layer12 is a polished surface, and is smoother than the bottom surface 12 bof the insulating layer 12. The top surface of the insulating layer 15including the photosensitive resin as the main component thereof, iseven smoother than the top surface 12 a of the insulating layer 12including the non-photosensitive thermosetting resin as the maincomponent thereof. For this reason, the line-and-space (L/S) of theinterconnect layer 16 can be made narrower than the line-and-space (L/S)of the interconnect layer 14. For example, the line-and-space (L/S) ofthe interconnect layer 14 may be 3 μm/3 μm, and the line-and-space (L/S)of the interconnect layer 16 may be 1 μm/1 μm. The same applies to theinterconnect layer 18 which will be described later.

The insulating layer 17 is formed on one surface of the insulating layer15, so as to cover the interconnect layer 16. A material used for theinsulating layer 17, and a thickness and a thermal expansion coefficientof the insulating layer 17, may be similar to those of the insulatinglayer 15. The insulating layer 17 may include a filler, such as silica(SiO₂) or the like.

The interconnect layer 18 is formed on one side of the insulating layer17, and is electrically connected to the interconnect layer 16. Theinterconnect layer 18 includes a via interconnect filling a via hole 17x which penetrates the insulating layer 17 to expose a top surface ofthe interconnect layer 16, and an interconnect pattern formed on the topsurface of the insulating layer 17. The via hole 17 x may be a recesshaving an inverted truncated cone shape. A diameter of a first openingof the via hole 17 x which opens at the insulating layer 19, may begreater than a diameter of a second opening of the via hole 17 x whichopens at the top surface of the interconnect layer 16. A bottom surfaceof the second opening of the via hole 17 x is formed by the top surfaceof the interconnect layer 16. The first opening of the via hole 17 x mayhave a diameter in a range of approximately 10 μm to approximately 20μm, for example. A material used for the interconnect layer 18, and athickness of the interconnect pattern forming the interconnect layer 18may be similar to those of the interconnect layer 14, for example. Theline-and-space (L/S) of the interconnect layer 18 may be similar to thatof the interconnect layer 16, for example.

The insulating layer 19 is formed on one surface of the insulating layer17, so as to cover the interconnect layer 18. In the second interconnectstructure 1H, the insulating layer 19 is an uppermost insulating layer.A material used for the insulating layer 19, and a thickness and athermal expansion coefficient of the insulating layer 19, may be similarto those of the insulating layer 15, for example. The insulating layer19 may include a filler, such as silica (SiO₂) or the like.

The thin film capacitor 20 is laminated to one surface of the insulatinglayer 19. The thin film capacitor 20 is a sheet capacitor having athickness of approximately 50 μm, and includes a dielectric 21, a firstelectrode 22, a second electrode 23, and an adhesive layer 24, forexample. The first electrode 22 is formed on one surface of thedielectric 21, and is connected to a ground of a circuit, for example.The second electrode 23 is formed on the other surface of the dielectric21, and is connected to a power supply of the circuit, for example. Theadhesive layer 24 is formed on the other surface of the dielectric 21,so as to cover the second electrode 23, and is bonded to the insulatinglayer 19. Examples of a material used for the dielectric 21 includebarium titanate or the like, for example. Examples of a material usedfor the first electrode 22 and the second electrode 23 include copper orthe like, for example.

The interconnect layer 31 is formed on one surface of thin filmcapacitor 20, and is electrically connected to the thin film capacitor20. In the second interconnect structure 1H, the interconnect layer 31is an uppermost interconnect layer. The interconnect layer 31 includes avia interconnect 32, and a plurality of pads 33 protruding from the topsurface side of the thin film capacitor 20. The via interconnect 32fills an inside of a via hole 20 x that penetrates the thin filmcapacitor 20, and fills an inside of a via hole 19 x that penetrates theinsulating layer 19 and exposes the top surface of the interconnectlayer 18.

The via interconnect 32 is formed continuously with the pad 33, and iselectrically connected to the interconnect layer 18. A portion of thevia interconnect 32 penetrates the dielectric 21 and the first electrode22 of the thin film capacitor 20, or the second electrode 23. and theadhesive layer 24 of the thin film capacitor 20. In other words, thefirst electrode 22 and the second electrode 23 are electricallyconnected to the interconnect layer 18 through the via interconnect 32.A large capacitor structure can be formed as a whole, by including thevia interconnect 32 that makes the electrical connection with theinterconnect layer 18 by penetrating the first electrode 22, and the viainterconnect 32 that makes the electrical connection by penetrating thesecond electrode 23.

The via hole 19 x may be a recess having an inverted truncated coneshape. A diameter of a first opening of the via hole 19 x which opens atthe adhesive layer 24 of the thin film capacitor 20, may be greater thana diameter of a second opening of the via hole 19 x which opens at thetop surface of the interconnect layer 18. A bottom surface of the secondopening of the via hole 19 x is formed by the top surface of theinterconnect layer 18. The first opening of the via hole 19 x may have adiameter in a range of approximately 10 μm to approximately 20 μm, forexample.

The via hole 20 x communicates with the via hole 19 x. The via hole 20 xhas a cylindrical shape with openings having an approximately constantdiameter. A diameter of the openings of the via hole 20 x is greaterthan the diameter of the first opening of the via hole 19 x. Thediameter of the openings the via hole 20 x may be in a range ofapproximately 20 μm to approximately 40 μm, for example.

A material used for the interconnect layer 31 may be similar to that ofthe interconnect layer 14, for example. A thickness of the interconnectlayer 31, that is, a sum of the thickness of the via interconnect 32 andthe thickness of the pad 33, may be approximately 10 μm, for example. Aplanar shape of the pad 33 may be a circular shape with a diameter of ina range of approximately 20 μm to approximately 30 μm, for example. Apitch of the pad 33 may be in a range of approximately 40 μm toapproximately 50 μm, for example. A size relationship between thediameter of the pad 33 and the diameter of the openings of the via hole20 x can be determined arbitrarily. A portion of the pad 33, that isexposed from the encapsulating resin layer 34, may be used as anexternal connection terminal for making electrical connection with asemiconductor chip.

A surface treatment layer 310, similar to the surface treatment layer110, may be formed on a top surface of the pad 33. In a case where aportion of a side surface and the top surface of the pad 33 protrudefrom the top surface 34 a of the encapsulating resin layer 34, thesurface treatment layer 310 is formed on only the top surface of the pad33, or on a portion of the side surface and the top surface of the pad33.

The encapsulating resin layer 34 is laminated on the thin film capacitor20, to expose the top surface of each pad 33, and to cover at least aportion of the side surface of each pad 33. The encapsulating resinlayer 34 may expose the top surface of the pad 33, and cover the entireside surface of the pad 33. In this case, the top surface of the pad 33coincides with the top surface 34 a of the encapsulating resin layer 34,for example. However, a portion of the side surface and the top surfaceof the pad 33 may protrude from the top surface 34 a of theencapsulating resin layer 34, and the top surface of the pad 33 may beexposed at a position recessed from the top surface 34 a of theencapsulating resin layer 34. In the case where a portion of the sidesurface and the top surface of the pad 33 protrude from the top surface34 a of the encapsulating resin layer 34, a spacing can be securedbetween the encapsulating resin layer 34 and the semiconductor chip, sothat an underfill resin can easily be filled between the encapsulatingresin layer 34 and the semiconductor chip.

Examples of a material used for the encapsulating resin layer 34 includea mold resin, for example. The mold resin is an insulating resinincluding a non-photosensitive thermosetting resin as a main componentthereof, which may be used for methods such as transfer molding,compression molding, injection molding, or the like. The mold resin isan insulating resin, such as a non-photosensitive thermosetting epoxyresin or the like, for example, and may include a filler similar to thatof the insulating layer 12, but does not include a reinforcing membersuch as glass fiber or the like.

From a viewpoint of reducing a warp of the wiring board 1, a thicknessof the encapsulating resin layer 34 is preferably greater than thethickness of the insulating layer 12. For example, when the thickness ofthe insulating layer 12 is in a range of 60 μm to 70 μm, the thicknessof the encapsulating resin layer 34 may be in a range of 80 μm to 150μm. A thermal expansion coefficient of the encapsulating resin layer 34is lower than the thermal expansion coefficient of each of theinsulating layers 15, 17, and 19. For sake of convenience ofdistinguishably illustrating the elements in the drawings, the thicknessof the encapsulating resin layer 34 in FIG. 1A is illustrated as if thethickness of the encapsulating resin layer 34 is smaller than thethickness of the insulating layer 12.

In addition, from the viewpoint of reducing the warp of the wiring board1, the thermal expansion coefficient of the encapsulating resin layer 34is preferably approximately the same as the thermal expansioncoefficient of the insulating layer 12. Herein, “approximately the same”means that the thermal expansion coefficient of the encapsulating resinlayer 34 is ±20% or less with respect to the thermal expansioncoefficient of the insulating layer 12.

For example, when the thermal expansion coefficient of the insulatinglayer 12 is in a range greater than or equal to 5 ppm/° C. and less thanor equal to 10 ppm/° C., the thermal expansion coefficient of theencapsulating resin layer 34 is preferably in a range greater than orequal to 5 ppm/° C. and less than or equal to 10 ppm/° C. The thermalexpansion coefficient of the encapsulating resin layer 34 may beadjusted to a predetermined value by a filler content, a composition ofthe insulating resin, or the like, for example.

[Method for Manufacturing Wiring Board according to First Embodiment]

Next, a method for manufacturing the wiring board according to the firstembodiment will be described. FIG. 2A through FIG. 7B are diagramsillustrating an example of a manufacturing process of the wiring boardaccording to the first embodiment. Although the manufacturing process ofone wiring board is illustrated in this example, the manufacturingprocess may form a plurality of parts which become wiring boards, andthereafter singulate the plurality of wiring boards to form each wiringboard. In addition, although the layer structure is formed only on oneside of a support in this example, the layer structure may be formed onboth the one side and the other side of the support.

First, in the process illustrated in FIG. 2A, a support 100 is prepared,the interconnect layer 11 and the insulating layer 12 are famed on thesupport 100, the via hole 12 x is formed in the insulating layer 12, anda laminated structure of a seed layer 131 and an electrolytic platinglayer 132 is formed on the insulating layer 12 inside the via hole 12 x.

The support 100 has a laminated structure in which a carrier-addedcopper film 104 is laminated on one side of a core substrate 101, forexample. The core substrate 101 is a resin substrate having a thicknessof approximately 0.7 mm, for example, and the resin substrate and mayinclude a reinforcing member, such as a glass fiber or the like. Thecarrier-added copper film 104 has a structure in which a thin film 104 amade of copper and having a thickness in a range of approximately 1.5 μmto approximately 5 μm, for example, is attached to a thick film (carrierfilm) 104 b made of copper and having a thickness in a range ofapproximately 10 μm to approximately 50 μm, for example, via a releaselayer (not illustrated), in a state where the thin film 104 a isstrippable. The thick film 104 b is provided as a support material tofacilitate handling of the thin film 104 a.

The structure of the support 100 described above is merely an example,and the structure of the support 100 is not particularly limited. Forexample, the support 100 may use a laminated body in which a pluralityof prepregs are laminated, in place of the core substrate 101. Inaddition, the support 100 may have a structure, in which thecarrier-added copper film 104 is arranged on one side of a substrate,such as a glass substrate, a metal substrate, or the like, via a releaselayer.

Once the support 100 is prepared, the interconnect layer 11 is firstformed on one side of the support 100. More particularly, a resist layerhaving an opening in a portion where the interconnect layer 11 is to beformed, is formed on the top surface of the carrier-added copper film104 (top surface of the thin film 104 a ) using a dry film resist or thelike. Then, the interconnect layer 11, which is an electrolytic platinglayer, is formed on the top surface of the carrier-added copper film 104exposed inside the opening, by electrolytic plating using thecarrier-added copper film 104 as a power feeding layer. The materialused for the interconnect layer 11, and the thickness of theinterconnect layer 11 are as described above. Thereafter, the resistlayer is stripped.

Next, the insulating layer 12 covering the interconnect layer 11 isformed on the top surface of the carrier-added copper film 104. Moreparticularly, a film of an insulating resin in a semi-cured state,including a non-photosensitive thermosetting resin as a main componentthereof, and a reinforcing member 128, is prepared. The insulating resinis then laminated to the top surface of the carrier-added copper film104, and is cured while being heated and pressed, to thereby form theinsulating layer 12. The material used for the insulating layer 12, andthe thickness, the thermal expansion coefficient, or the like of theinsulating layer 12, are as described above.

Next, the via hole 12 x, that penetrates the insulating layer 12 andexposes the top surface of the interconnect layer 11, is formed in theinsulating layer 12. The via hole 12 x may be formed by a laser beammachining using a CO₂ laser, a YAG laser, an excimer laser, or the like,for example. After forming the via hole 12 x, a desmear treatment ispreferably performed to remove resin residue adhered to the surface ofthe interconnect layer 11 exposed at the bottom of each via hole 12 x.

Next, a laminated structure of the seed layer 131 and the electrolyticplating layer 132 is formed on the top surface 12 a of the insulatinglayer 12 inside the via hole 12 x, using a semi-additive method, forexample. More particularly, the seed layer 131 is first formed on thetop surface 12 a of the insulating layer 12, the inner sidewall surfaceof the via hole 12 x, and the top surface of the interconnect layer 11exposed inside the via hole 12 x, by electroless plating or sputtering.A copper layer having a thickness in a range of approximately 100 nm toapproximately 350 nm, for example, may be used for the seed layer 131.In addition, a laminated layer in which a titanium layer having athickness in a range of approximately 20 nm to approximately 50 nm, anda copper layer having a thickness of approximately 100 nm toapproximately 300 nm, for example, are laminated in this order, may beused for the seed layer 131. By forming the titanium layer in a lowerlayer portion of the seed layer 131, it is possible to improve theadhesion between the insulating layer 12 and the interconnect layer 13.Titanium nitride or the like may be used in place of the titaniumforming the lower layer portion of the seed layer 131. Titanium andtitanium nitride are metals having a higher corrosion resistance thancopper. Then, the electrolytic plating layer (for example, a copperlayer) 132 is formed on the seed layer 131 by electrolytic plating usingthe seed layer 131 as a power feeding layer.

Next, in the process illustrated in FIG. 2B, a top surface of thelaminated structure of the seed layer 131 and the electrolytic platinglayer 132 illustrated in FIG. 2A is polished to expose the top surface12 a of the insulating layer 12, thereby forming the interconnect layer13 which is the via interconnect filling the via hole 12 x. A ChemicalMechanical Polishing (CMP) or the like, for example, may be used for thepolishing of the interconnect layer 13. The top surface of theinterconnect layer 13 may coincide with the top surface 12 a of theinsulating layer 12, for example.

When polishing the interconnect layer 13, a portion of the top surface12 a of the insulating layer 12 may be polished and removedsimultaneously therewith. By polishing the top surface 12 a of theinsulating layer 12 together with the interconnect layer 13 and removinga portion of the top surface 12 a of the insulating layer 12, theroughness of the top surface 12 a of the insulating layer 12 can bereduced compared to that before the polishing. In other words, it ispossible to improve the smoothness of the top surface 12 a of theinsulating layer 12. The roughness Ra of the top surface 12 a of theinsulating layer 12 before performing the CMP (before polishing) is in arange of approximately 300 nm to approximately 400 nm, for example.After performing the CMP, the roughness Ra of the top surface 12 a ofthe insulating layer 12 is in a range of approximately 15 nm toapproximately 40 nm. Accordingly, by reducing the roughness andimproving the smoothness of the top surface 12 a of the insulating layer12, it becomes possible to form a fine-line interconnect (interconnectlayer having a high interconnect density) at a later stage of themanufacturing process. The roughness Ra of the bottom surface 12 b ofthe insulating layer 12 is in a range of approximately 180 nm toapproximately 280 nm, for example.

Next, in the process illustrated in FIG. 2C, the interconnect layer 14having a predetermined pattern is formed on the top surface of theinterconnect layer 13 and the top surface 12 a of the insulating layer12. The interconnect layer 14 may be formed using a semi-additivemethod, similar to the interconnect layer 13. More particularly, a seedlayer is first formed by electroless plating or sputtering, so as tocontinuously cover the top surface of the interconnect layer 13 and thetop surface 12 a of the insulating layer 12. Although the electrolessplating may be used to form the seed layer, it is more advantageous touse the sputtering from a viewpoint of increasing the density of theinterconnect layer, because the seed layer can be made thinner by thesputtering.

Then, a photosensitive resist layer is formed on the entire top surfaceof the seed layer, and the resist layer is exposed and developed, tothereby form an opening exposing a portion where the interconnect layer14 is to be formed. Next, an electrolytic plating layer is foisted onthe top surface of the seed layer exposed inside the opening, byelectrolytic plating using the seed layer as a power feeding layer.Then, after stripping the resist layer, the electrolytic plating layeris used as a mask, to remove a portion of the seed layer not covered bythe electrolytic plating layer by etching. Hence, the interconnect layer14, having the electrolytic plating layer laminated on the seed layer,is formed. The material used for the interconnect layer 14, and thethickness, the line-and-space (L/S), or the like of the interconnectlayer 14, are as described above. Although the interconnect layer 14 hasthe laminated structure in which the electrolytic plating layer islaminated on the seed layer, illustration of the seed layer and theelectrolytic plating layer in a distinguishable manner is omitted (thesame may apply to other interconnect layers) in FIG. 2C or the like.

Next, in the process illustrated in FIG. 3A, after a photosensitiveresin in a liquid or paste form is coated on the top surface 12 a of theinsulating layer 12 so as to cover the interconnect layer 14, thephotosensitive resin is heated to a temperature that does not causecomplete curing of the photosensitive resin, to thereby form thesemi-cured insulating layer 15. The material used for the insulatinglayer 15, and thickness of the insulating layer 15 are as describedabove. Next, after feinting the via hole 15 x by photolithography, forexample, the insulating layer 15 is heated to a temperature higher thanor equal to a curing temperature of the photosensitive resin, so as tocure the insulating layer 15. The top surface of the insulating layer 15including the photosensitive resin as the main component thereof is evensmoother than the top surface 12 a of the insulating layer 12. Theroughness Ra of the top surface of the insulating layer 15 may be in arange of approximately 2 nm to approximately 6 nm, for example.

Next, in the process illustrated in FIG. 3B, the interconnect layer 16,the insulating layer 17, the interconnect layer 18, and the insulatinglayer 19 are formed by repeating processes similar to those illustratedin FIG. 2C and FIG. 3A. Thereafter, the via hole 19 x, that penetratesthe insulating layer 19, and exposes the top surface of the interconnectlayer 18 inside the via hole 19 x, is formed. In processes illustratedin FIG. 4A through FIG. 6B which will be described later, a descriptionwill be given with reference to an enlarged vide of a part A illustratedin FIG. 3B.

Next, in the process illustrated in FIG. 4A, the thin film capacitor 20is prepared, and a plurality of via holes 20 x is formed in the thinfilm capacitor 20 by laser beam machining or the like. The plurality ofvia holes 20 x includes at least a via hole that opens the firstelectrode 22, and a via hole that opens the second electrode 23. Thediameters of each of the via holes 20 x do not necessarily have to bethe same.

Next, in the process illustrated in FIG. 4B, the thin film capacitor 20is arranged on the insulating layer 19, in a state where the adhesivelayer 24 faces the insulating layer 19. In this case, the via hole 19 xand the via hole 20 x communicate with each other. Then, the adhesivelayer 24 is cured by a heat treatment or the like, to fix the thin filmcapacitor 20, on the insulating layer 19.

Next, in the processes illustrated in FIG. 4C through FIG. 5C, theinterconnect layer 31 is formed by a semi-additive method, for example.First, as illustrated in FIG. 4C, a seed layer 311 is formed on the topsurface of the dielectric 21, the top surface and the side surface ofthe first electrode 22, inner surfaces defining the vias holes 19 x and20 x, respectively, and the top surface of the interconnect layer 18exposed inside the via holes 19 x, by electroless plating or sputtering.The seed layer 311 may be a copper layer having a thickness in a rangeof approximately 100 nm to approximately 350 nm, for example.

Next, in the process illustrated in FIG. 5A, a photosensitive resistlayer 500 is formed on the seed layer 311, the resist layer 500 isexposed and developed, and an opening 500 x is formed to expose aportion where the interconnect layer 31 is to be formed. The resistlayer 500 can be formed by laminating a dry film resist on the seedlayer 311, for example.

Next, in the process illustrated in FIG. 5B, an electrolytic platinglayer 312 (for example, a copper layer) is formed on the seed layer 311exposed inside the opening 500 x, by electrolytic plating utilizing theseed layer 311 as a power feeding layer. Further, in the processillustrated in. FIG. 5C, after the resist layer 500 is stripped, theelectrolytic plating layer 312 is used as a mask, and a portion of theseed layer 311, that is not covered by the electrolytic plating layer312, is removed by etching. Hence, the interconnect layer 31, formedfrom the seed layer 311 and the electrolytic plating layer 312illustrated in FIG. 5B, and including the via interconnect 32 that fillsthe insides of the via holes 19 x and 20 x, and the pad 33 protrudingfrom the top surface side of the thin film capacitor 20, is formed.

Next, in the process illustrated in FIG. 6A, the encapsulating resinlayer 34 is formed on the thin film capacitor 20, so as to cover the topsurface and the side surface of the pad 33 of the interconnect layer 31.The encapsulating resin layer 34 may be formed by mold forming using amold resin, for example. For example, the structure illustrated in FIG.5C is accommodated within a mold, and the fluidized mold resin isintroduced into the mold by applying a pressure in a range of 5 MPa to10 MPa, for example. Thereafter, the mold resin is heated to atemperature of approximately 180° C. and cured, to thereby form theencapsulating resin layer 34. After the required encapsulation processis completed, the structure covered with the encapsulating resin layer34 is removed from the mold. The mold forming may use transfer molding,compression molding, injection molding, or the like, for example.

Next, in the process illustrated in FIG. 6B, top surface of theencapsulating resin layer 34 illustrated in FIG. 6A is polished, toexpose at least the top surface of the pad 33. The CMP or the like, forexample, may be used to polish the encapsulating resin layer 34. The topsurface of the pad 33 may coincide with the top surface 34 a of theencapsulating resin layer 34, for example. However, by adjusting apolishing amount of the encapsulating resin layer 34 or the like, aportion of the side surface and the top surface of the pad 33 mayprotrude from the top surface 34 a of the encapsulating resin layer 34,or the top surface of the pad 33 may be exposed at a more recessedposition than the top surface 34 a of the encapsulating resin layer 34.

Next, in the process illustrated in FIG. 7A, an outer periphery of theentire structure illustrated in FIG. 6B is cut using a dicing blade orthe like. Next, in the process illustrated in FIG. 7B, the support 100illustrated in FIG. 7A is removed, the surface treatment layer 310 isfarmed on the top surface of the pad 33, as required, and the surfacetreatment layer 110 is formed on the bottom surface of the interconnectlayer 11, as required. In order to remove the support 100, the coresubstrate 101 and thick film 104 b are first mechanically stripped fromthe thin film 104 a. Then, the thin film 104 a is removed by wet etchingusing an aqueous ferric chloride solution, an aqueous copper chloridesolution, an aqueous ammonium persulfate solution, or the like, forexample. In this state, when the interconnect layer 11 is made ofcopper, the bottom surface of the interconnect layer 11 is also etched,and the bottom surface of the interconnect layer 11 becomes recessedfrom the bottom surface 12 b of the insulating layer 12 toward theinterconnect layer 13. The surface treatment layers 110 and 310 may be ametal layer or a laminated structure of metal layers described aboveformed by electroless plating, for example, or may be formed by ananti-oxidation treatment, such as the OSP treatment or the like.

As described above, in the wiring board 1, the thin film capacitor 20 isdisposed immediately under the pad 33. Because the pad 33 is used as theexternal connection terminal for making electrical connection with thesemiconductor chip, when the semiconductor chip is mounted on the wiringboard 1, the thin film capacitor 20 is arranged at a position close tothe semiconductor chip. For this reason, it is possible to reduce anequivalent series inductance of the thin film capacitor 20, and enablethe semiconductor chip to operate at a high frequency of 100 MHz orhigher, for example.

Moreover, in the wiring board 1, the encapsulating resin layer 34 islaminated on the thin film capacitor 20, so as to expose the top surfaceof the pad 33, and to cover at least a portion of the side surface ofthe pad 33. When mounting the semiconductor chip on the wiring board 1,the pad 33 and an electrode pad of the semiconductor chip are connectedby a solder. If the thin film capacitor were exposed at the surface ofthe wiring board, there is a risk of the thin film capacitor crackingdue to thermal stress and pressure generated when mounting thesemiconductor chip. However, because the wiring board 1 has a structurein which the encapsulating resin layer 34 is laminated on the thin filmcapacitor 20, it is possible to reduce damage to the thin film capacitor20 by this structure which reduces the thermal stress and pressuregenerated when mounting the semiconductor chip from easily affecting thethin film capacitor 20.

In the wiring board 1, because the top surface of the encapsulatingresin layer 34 is polished to expose the top surface of the pad 33,heights of the top surfaces of the plurality of pads 33 become uniform.Here, a uniform height of the pads refers to a case where the height ofa highest pad is +10 μm with respect to the height of a lowest pad. Inaddition, because the plurality of pads 33 exposed from theencapsulating resin layer 34 has a uniform top surface area and apolished smooth surface, wetting and spread of the solder becomeconstant when mounting the semiconductor chip, to thereby improve amounting reliability of the semiconductor chip. Here, a uniform topsurface area of the pads refers to a case where a largest top surfacearea of the pad is +20% with respect to a smallest top surface area ofthe pad.

Because the conventional wiring board does not polish the pads by CMP,the height of the pads vary. Moreover, in the conventional wiring board,the entire side surface of the pad is exposed. For this reason, thewetting and spreading of the solder extend to the side surface of thepads having a low height, thereby causing a problem such as aninsufficient amount of solder on the top surface of the pads, or thelike. In contract, such a problem is eliminated according to the wiringboard 1.

Further, in the wiring board 1, the first interconnect structure itincluding the insulating layer 12 having the non-photosensitivethermosetting resin as the main component thereof, and the encapsulatingresin layer 34 having the non-photosensitive thermosetting resin as themain component thereof, are disposed on both sides of the secondinterconnect structure 1H including the insulating layers 15, 17, and 19having the photosensitive resin as the main component thereof, tosandwich the 20 second interconnect structure 1H therebetween. Thethermal expansion coefficient of the insulating layer 12 and the thermalexpansion coefficient of the encapsulating resin layer 34 are lower thanthe thermal expansion coefficient of each of the insulating layers 15,17, and 19. Because this structure improves the imbalance of the thermalexpansion coefficients in the thickness direction of the wiring board 1,it is possible to reduce the warp of the wiring board 1.

In addition, because the warp of the wiring board 1 is reduced, it iseasy to mount the semiconductor chip on the side of the wiring board 1provided with the encapsulating resin layer 34, and to mount the wiringboard 1 on other wiring boards.

The structure in the state illustrated in FIG. 7A before the cutting maybe the form in which the wiring board is forwarded. In other words, thewiring board 1 may be forwarded in the state including the support 100.

First Application Example of First Embodiment

A first application example of the first embodiment illustrates anexample of a laminated wiring board in which the wiring board accordingto the first embodiment is mounted on another wiring board. In the firstapplication example of the first embodiment, a description ofconstituent elements that are the same as those of the embodimentalready described above may be omitted.

FIG. 8 is a cross sectional view illustrating the laminated wiring boardaccording to the first application example of the first embodiment. Asillustrated in FIG. 8, a laminated wiring board 3 is a multi-layer (ormulti-level) wiring board including the wiring board 1 mounted on awiring board 2.

The wiring board 2 is a multi-layer wiring board having an interconnectlayer and an insulating layer laminated on both surfaces of a core layer50, and may be manufactured by a known build-up method, for example.Each interconnect layer of the wiring board 2 has a lower interconnectdensity (or wider line-and-space (L/S)) than the interconnect layers 14,16, 18, and 31 of the wiring board 1. The line-and-space (L/S) of eachinterconnect layer of the wiring board 2 may be approximately 20 μm/20μm, for example.

In the wiring board 2, an interconnect layer 52, an insulating layer 53,an interconnect layer 54, an insulating layer 55, an interconnect layer56, a solder resist layer 57, and an interconnect layer 58 aresuccessively laminated on one surface of the core layer 50. In addition,an interconnect layer 62, an insulating layer 63, an interconnect layer64, an insulating layer 65, an interconnect layer 66, and a solderresist layer 67 are successively laminated on the other surface of thecore layer 50.

A so-called glass epoxy substrate or the like, including glass clothimpregnated with an insulating resin, such as an epoxy-based resin orthe like, may be used for the core layer 50. A substrate or the like,including unwoven or woven fabric, such as glass fiber, carbon fiber,aramid fiber, or the like, impregnated with an epoxy-based resin, apolyimide-based resin, or the like, may also be used for the core layer50. The core layer 50 may have a thickness in a range of approximately60 μm to approximately 400 μm, for example. The core layer 50 includes athrough hole 50 x that penetrates the core layer 50 in a thicknessdirection thereof. A planar shape of the through hole 50 x may be acircular shape, for example.

An interconnect layer 52 is formed on one surface of the core layer 50.In addition, an interconnect layer 62 is formed on the other surface ofthe core layer 50. The interconnect layer 52 and the interconnect layer62 are electrically connected through a penetrating interconnect 51formed inside the through hole 50 x. The interconnect layers 52 and 62are patterned into predetermined planar shapes, respectively. Examplesof a material used for the interconnect layers 52 and 62 and thepenetrating interconnect 51 include copper (Cu) or the like, forexample. The interconnect layers 52 and 62 may have a thickness in arange of approximately 10 μm to approximately 30 μm, for example. Theinterconnect layer 52, the interconnect layer 62, and the penetratinginterconnect 51 may be integrally formed.

An insulating layer 53 is formed on one surface of the core layer 50, soas to cover the interconnect layer 52. Examples of a material used forthe insulating layer 53 include non-photosensitive thermosettinginsulating resins including an epoxy-based resin or a polyimide-basedresin as a main component thereof, for example. The insulating layer 53may have a thickness in a range of approximately 30 μm to approximately40 μm, for example. The insulating layer 53 may include a filler, suchas silica (SiO₂) or the like.

An interconnect layer 54 is formed on one surface of the insulatinglayer 53. The interconnect layer 54 includes a via interconnect fillinginside a via hole 53 x that penetrates the insulating layer 53 to exposea top surface of interconnect layer 52, and an interconnect patternformed on a top surface of insulating layer 53. The interconnect patternforming the interconnect layer 54 is electrically connected to theinterconnect layer 52 through the via interconnect. The via hole 53 xmay be a recess having an inverted truncated cone shape. A diameter of afirst opening of the via hole 53 x which opens at the insulating layer55, may be greater than a diameter of a second opening of the via hole53 x which opens at the top surface of the interconnect layer 52. Abottom surface of the second opening of the via hole 53 x is formed bythe top surface of the interconnect layer 52. A material used for theinterconnect layer 54 and a thickness of the interconnect pattern of theinterconnect layer 54 may be similar to those of the interconnect layer52, for example.

An insulating layer 55 is famed on a top surface of the insulating layer53, so as to cover the interconnect layer 54. A material used for theinsulating layer 55 and a thickness of the insulating layer 55 may besimilar to those of the insulating layer 53, for example. The insulatinglayer 55 may include a filler, such as silica (SiO₂) or the like.

An interconnect layer 56 is formed on one surface of the insulatinglayer 55. The interconnect layer 56 includes a via interconnect fillinginside a via hole 55 x that penetrates the insulating layer 55 to exposea top surface of interconnect layer 54, and an interconnect patternformed on a top surface of insulating layer 55. The interconnect patternforming the interconnect layer 56 is electrically connected to theinterconnect layer 54 through the via interconnect. The via hole 55 xmay be a recess having an inverted truncated cone shape. A diameter of afirst opening of the via hole 55 x which opens at the solder resistlayer 57, may be greater than a diameter of a second opening of the viahole 55 x which opens at the top surface of the interconnect layer 54. Abottom surface of the second opening of the via hole 55 x is formed bythe top surface of the interconnect layer 54. A material used for theinterconnect layer 56 and a thickness of the interconnect pattern of theinterconnect layer 56 may be similar to those of the interconnect layer52, for example.

The solder resist layer 57 is formed on the top surface of insulatinglayer 55, so as to cover the interconnect layer 56. The solder resistlayer 57 may be formed from a photosensitive resin, such as anepoxy-based resin, an acrylic-based resin, or the like, for example. Thesolder resist layer 57 may have a thickness in a range of approximately15 μm to approximately 35 μm, for example.

The interconnect layer 58 is formed on one surface of the solder resistlayer 57. The interconnect layer 58 includes a via interconnect fillinginside a via hole 57 x that penetrates the solder resist layer 57 toexpose a top surface of interconnect layer 56, and pads formed on a topsurface of solder resist layer 57. The pad forming the interconnectlayer 58 is electrically connected to the interconnect layer 56 throughthe via interconnect. The via hole 57 x may be a recess having aninverted truncated cone shape. A diameter of a first opening of the viahole 57 x which opens at the wiring board 1, may be greater than adiameter of a second opening of the via hole 57 x which opens at the topsurface of the interconnect layer 56. A bottom surface of the secondopening of the via hole 57 x is formed by the top surface of theinterconnect layer 56. A material used for the interconnect layer 58 anda thickness of the interconnect pattern of the interconnect layer 58 maybe similar to those of the interconnect layer 52, for example. A planarshape of the pad forming the interconnect layer 58 may be a circularshape, for example. A surface treatment layer described above may beformed on the surface (only on the top surface, or on the top surfaceand the side surface) of the pad forming the interconnect layer 58, asrequired.

The insulating layer 63 is formed on the other surface of the core layer50, so as to cover the interconnect layer 62. A material used for theinsulating layer 63 and a thickness of the insulating layer 63 may besimilar to those of the insulating layer 53, for example. The insulatinglayer 63 may include a filler, such as silica (SiO₂) or the like.

The interconnect layer 64 is formed on the other surface of theinsulating layer 63. The interconnect layer 64 includes a viainterconnect filling inside a via hole 63 x that penetrates theinsulating layer 63 to expose a bottom surface of interconnect layer 62,and an interconnect pattern formed on a bottom surface of insulatinglayer 63. The interconnect pattern forming the interconnect layer 64 iselectrically connected to the interconnect layer 62 through the viainterconnect. The via hole 63 x may be a recess having an invertedtruncated cone shape. A diameter of a first opening of the via hole 63 xwhich opens at the insulating layer 65, may be greater than a diameterof a second opening of the via hole 63 x which opens at the bottomsurface of the interconnect layer 62. A bottom surface of the secondopening of the via hole 63 x is formed by the bottom surface of theinterconnect layer 62. A material used for the interconnect layer 64 anda thickness of the interconnect pattern of the interconnect layer 64 maybe similar to those of the interconnect layer 52, for example.

The insulating layer 65 is formed on the bottom surface of theinsulating layer 63, so as to cover the interconnect layer 64. Amaterial used for the insulating layer 65 and a thickness of theinsulating layer 65 may be similar to those of the insulating layer 53,for example. The insulating layer 65 may include a filler, such assilica (SiO₂) or the like.

The interconnect layer 66 is formed on the other surface of theinsulating layer 65. The interconnect layer 66 includes a viainterconnect filling inside a via hole 65 x that penetrates theinsulating layer 65 to expose a bottom surface of interconnect layer 64,and an interconnect pattern formed on a bottom surface of insulatinglayer 65. The interconnect pattern forming the interconnect layer 66 iselectrically connected to the interconnect layer 64 through the viainterconnect. The via hole 65 x may be a recess having an invertedtruncated cone shape. A diameter of a first opening of the via hole 65 xwhich opens at the solder resist layer 67, may be greater than adiameter of a second opening of the via hole 65 x which opens at thebottom surface of the interconnect layer 64. A bottom surface of thesecond opening of the via hole 65 x is famed by the bottom surface ofthe interconnect layer 64. A material used for the interconnect layer 66and a thickness of the interconnect pattern of the interconnect layer 66may be similar to those of the interconnect layer 52, for example.

The solder resist layer 67 is formed on the bottom surface of insulatinglayer 65, so as to cover interconnect layer 66. A material used for thesolder resist layer 67 and a thickness of the solder resist layer 67 maybe similar to those of the solder resist layer 57, for example. Thesolder resist layer 67 has an opening 67 x, and a portion of the bottomsurface of interconnect layer 66 is exposed inside the opening 67 x. Aplanar shape of the opening 67 x may be a circular shape, for example.The interconnect layer 66, that is exposed inside the opening 67 x, canbe used as a pad for making electrical connection with a mounting boardor package (not illustrated), such as a motherboard or the like. Thesurface treatment layer described above may be formed on the bottomsurface of the interconnect layer 66 that is exposed inside the opening67 x, as required.

The wiring board 1 is mounted on the wiring board 2. More particularly,the surface treatment layer 110 of the wiring board 1, and theinterconnect layer 58 forming an external connection terminal of thewiring board 2, are bonded by a solder layer 41 that solidifies aftermelting. An underfill resin 42 is filled between the bottom surface ofthe wiring board 1 (the bottom surface of the insulating layer 12) andthe top surface of the wiring board 2 (the top surface of the solderresist layer 57), and the underfill resin 42 also covers a portion ofthe side surface of the wiring board 1, to thereby bond the wiring board1 and the wiring board 2 to each other.

A stiffener 70 is attached to an outer periphery of the top surface ofthe wiring board 2 (the top surface of the solder resist layer 57). Thestiffener 70 has a planar shape that is a picture-frame shape, forexample. The stiffener 70 is provided to reinforce the strength of theentire laminated wiring board 3, and to reduce a warp that occurs whenmounting the laminated wiring board 3 on the motherboard or the like. Amaterial used for the stiffener 70 may be SUS 304 (stainless steelincluding Cr and Ni as main components thereof: 0.08C-18Cr-8Ni) or thelike, for example. The material used for the stiffener 70 may also be ametal plate made of copper, copper alloy, or the like, and a resinplate, such as a glass epoxy substrate or the like. The stiffener 70 maybe provided, as required.

As described above, by mounting the wiring board 1 that includes theinterconnect layers having the high interconnect density on the wiringboard 2 that includes the interconnect layers having the lowinterconnect density, it is possible to easily manufacture the laminatedwiring board 3 that can be mounted with the semiconductor chip.

Further, because the wiring board 1 has a small warp, there is littlevariation in the distance between the interconnect layer 11 of eachwiring board 1 and the interconnect layer 58 of the wiring board 2opposing the interconnect layer 11. For this reason, it is possible toimprove a connection reliability of the interconnect layer 11 and theinterconnect layer 58 through the solder layer 41.

Second Application Example of First Embodiment

A second application example of the first embodiment illustrates anexample of a semiconductor device in which a semiconductor chip ismounted on the laminated wiring board according to the first applicationexample of the first embodiment. In the second application example ofthe first embodiment, the description of the same component as that ofthe embodiment described above may be omitted.

FIG. 9 is a cross sectional view illustrating an example of thesemiconductor device according to the second application example of thefirst embodiment. As illustrated in FIG. 9, a semiconductor device 5includes the laminated wiring board 3 illustrated in FIG. 8, asemiconductor chip 80, a bump 90, and an underfill resin 95. A pluralityof semiconductor chips 80 are flip-chip bonded to the laminated wiringboard 3.

The semiconductor chip 80 has a semiconductor integrated circuit (notillustrated) or the like formed on a thin semiconductor substrate 81made of silicon or the like, for example. An electrode pad 82 is formedon a circuit forming surface of the semiconductor substrate 81, and thiselectrode pad 82 electrically connected to the semiconductor integratedcircuit (not illustrated). The circuit forming surface of thesemiconductor substrate 81 is an area in which one or more circuits areformed.

The electrode pad 82 of the semiconductor chip 80 is electricallyconnected to the surface treatment layer 310 of the laminated wiringboard 3 through the bump 90. The underfill resin 95 is filled betweenthe circuit forming surface of the semiconductor chip 80 and the topsurface of the wiring board 1, and also covers a side surface of thesemiconductor chip 80. The bump 90 is a solder bump, for example.Examples of a material used for the solder bump include SnBi solder orthe like, for example.

Each of the semiconductor chips 80 may have the same size or havedifferent sizes. In addition, each of the semiconductor chips 80 mayhave the same function or have different functions. Examples of thefunction of the semiconductor chip 80 include a memory (Dynamic RandomAccess Memory (DRAM) or the like), a logic circuit (Central ProcessingUnit (CPU) or the like), or the like. Moreover, one or two semiconductorchips 80 may be mounted on the laminated wiring board 3, or four or moresemiconductor chips 80 may be mounted on the laminated wiring board 3.

As described above, the semiconductor device 5 can be obtained bymounting the semiconductor chips 80 on the laminated wiring board 3according to the first application example according to the firstembodiment. Because the semiconductor chips 80 are mounted on the wiringboard 1 that includes the interconnect layers having the highinterconnect density, the semiconductor chips 80 can easily be connectedto each other by the interconnect patterns having the high interconnectdensity, to thereby enable exchange of signals among the semiconductorchips 80. Further, in the wiring board 1 forming the semiconductordevice 5, because the thin film capacitor 20 is disposed immediatelyunder the pad 33 near the semiconductor chip 80, it is possible toreduce the equivalent series inductance of the thin film capacitor 20,and enable the semiconductor chip 80 to operate at a high frequency.

First Modification of First Embodiment

A first modification of the first embodiment illustrates an example inwhich the thin film capacitor is provided on the wiring board 2. In thefirst modification of the first embodiment, a description of constituentelements that are the same as those of the embodiment already describedabove may be omitted.

FIG. 10 is a cross sectional view illustrating an example of the wiringboard according to the first modification of the first embodiment. In awiring board 6 illustrated in FIG. 10, the solder resist layer 57 isreplaced by an insulating layer 57A, and a thin film capacitor 20, theinterconnect layer 31 and the encapsulating resin layer 34 are providedon an insulating layer 57A in place of the interconnect layer 58, in thewiring board 2 illustrated in FIG. 8. The insulating layer 57A is formedof a non-photosensitive thermosetting insulating resin, similar to theinsulating layer 53. The interconnect layer 31 is electrically connectedto the interconnect layer 56 through the via interconnect 32 inside thevia hole 20 x and the via hole 57 x that communicates with via holes 20x. When forming the via hole 57 x in the insulating layer 57A, laserbeam machining method may be used, for example.

Accordingly, the thin film capacitor 20 may be provided on thephotosensitive insulating resin, such as the wiring board 1, or on thenon-photosensitive thermosetting insulating resin, such as the wiringboard 6. In the wiring board 6, a semiconductor chip can be mounted onthe encapsulating resin layer 34.

In the wiring board 6, the thin film capacitor 20 is disposedimmediately under the pad 33, similar to the wiring board 1. Because thepad 33 is used as the external connection terminal for making electricalconnection with the semiconductor chip, when the semiconductor chip ismounted on the wiring board 6, the thin film capacitor 20 is disposed ata position near the semiconductor chip. For this reason, it is possibleto reduce the equivalent serial inductance of the thin film capacitor20, and enable the semiconductor chip to operate at a high frequency.

In addition, in the wiring board 6, due to the provision of theencapsulating resin layer 34 that is laminated on the thin filmcapacitor 20, the structure reduces the thermal stress and pressuregenerated when mounting the semiconductor chip from easily affecting thethin film capacitor 20, similar to the wiring board 1, to thereby reducedamage to the thin film capacitor 20. Moreover, in the wiring board 6,the wetting and spread of the solder become constant when mounting thesemiconductor chip, similar to the wiring board 1, to thereby improvethe mounting reliability of the semiconductor chip.

According to each of the embodiments and application examples describedabove, it is possible to provide a wiring board capable of reducingdamage to a thin film capacitor.

Various aspects of the subject matter described herein may be set outnon-exhaustively in the following numbered clauses:

1. A method for manufacturing a wiring board, comprising:

laminating a thin film capacitor on an insulating layer;

forming an interconnect layer electrically connected to the thin filmcapacitor; and

laminating an encapsulating resin layer on the thin film capacitor,wherein

the interconnect layer includes a pad protruding from the thin filmcapacitor,

the encapsulating resin layer is a mold resin including anon-photosensitive thermosetting resin as a main component thereof, and

the laminating the encapsulating resin layer includes

forming the encapsulating resin layer so as to cover a top surface and aside surface of the pad, and

polishing a top surface of the encapsulating resin layer to expose thetop surface of the pad.

2. The method for manufacturing the wiring board according to clause 1,wherein the interconnect layer includes a via interconnect, that isformed continuously with the pad, and penetrates the thin film capacitorand the insulating layer.

3. The method for manufacturing the wiring board according to clause 2,wherein

the thin film capacitor has a dielectric, and an electrode provided onthe dielectric, and

the interconnect layer includes a via interconnect penetrating thedielectric and the electrode.

4. The method for manufacturing the wiring board according to clause 3,wherein

the interconnect layer includes a plurality of pads protruding from thethin film capacitor,

the electrode includes a first electrode provided on a first surface ofthe dielectric, and a second electrode provided on a second surface ofthe dielectric opposite to the first surface of the dielectric,

at least one of the plurality of the pads has a first via interconnectpenetrating the first electrode, and

at least one of the plurality of pads has a second via interconnectpenetrating the second electrode.

5. The method for manufacturing the wiring board according to clause 4,wherein the plurality of pads has a uniform height.

Although the application examples are numbered with, for example,“first,” or “second,” the ordinal numbers do not imply priorities of theapplication example. Many other variations and modifications will beapparent to those skilled in the art.

All examples and conditional language recited herein are intended forpedagogical purposes to aid the reader in understanding the inventionand the concepts contributed by the inventor to furthering the art, andare to be construed as being without limitation to such specificallyrecited examples and conditions, nor does the organization of suchexamples in the specification relate to a showing of the superiority andinferiority of the invention. Although the embodiments of the presentinvention have been described in detail, it should be understood thatthe various changes, substitutions, and alterations could be made heretowithout departing from the spirit and scope of the invention.

What is claimed is:
 1. A wiring board comprising: an insulating layer; athin film capacitor laminated on the insulating layer; an interconnectlayer electrically connected to the thin film capacitor; and anencapsulating resin layer laminated on the thin film capacitor, whereinthe interconnect layer includes a pad protruding from the thin filmcapacitor, the encapsulating resin layer is a mold resin having anon-photosensitive thermosetting resin as a main component thereof, andthe encapsulating resin layer exposes a top surface of the pad, andcovers at least a portion of a side surface of the pad.
 2. The wiringboard as claimed in claim 1, wherein the interconnect layer includes avia interconnect, that is formed continuously with the pad, andpenetrates the thin film capacitor and the insulating layer.
 3. Thewiring board as claimed in claim 2, wherein the thin film capacitor hasa dielectric, and an electrode provided on the dielectric, and theinterconnect layer includes a via interconnect penetrating thedielectric and the electrode.
 4. The wiring board as claimed in claimwherein the interconnect layer includes a plurality of pads protrudingfrom the thin film capacitor, the electrode includes a first electrodeprovided on a first surface of the dielectric, and a second electrodeprovided on a second surface of the dielectric opposite to the firstsurface of the dielectric, at least one of the plurality of the pads hasa first via interconnect penetrating the first electrode, and at leastanother of the plurality of pads has a second via interconnectpenetrating the second electrode.
 5. The wiring board as claimed inclaim 4, wherein the plurality of pads has a uniform height.
 6. Thewiring board as claimed in claim 4, wherein the plurality of pads has auniform top surface area.
 7. The wiring board as claimed in claim 4,wherein a top surface of the plurality of pads protrudes from theencapsulating resin layer.
 8. The wiring board as claimed in claim 4,wherein the plurality of pads is an external connection terminal formaking electrical connection with a semiconductor chip.
 9. The wiringboard as claimed in claim 1, wherein the insulating layer includes aphotosensitive resin as a main component thereof.
 10. The wiring boardas claimed in claim 1, further comprising: a surface treatment layerformed on the top surface of the pad.
 11. The wiring board as claimed inclaim 2, wherein the via interconnect penetrates the thin film capacitorwith a first diameter, and penetrates the insulating layer with a seconddiameter, and the first diameter is greater than the second diameter.12. The wiring board as claimed in claim 3, wherein the thin filmcapacitor further has an adhesive layer, the dielectric is connected tothe insulating layer through the adhesive layer, and the viainterconnect penetrates the adhesive layer.